1. Field of the Invention
The present invention relates, in general, to semiconductor flash memory devices and, more particularly, to semiconductor flash memory devices and methods of fabricating the same that can reduce an electron trap phenomenon after a sidewall oxide layer of a gate electrode is formed.
2. Description of the Related Art
In general, data stored in a semiconductor flash memory device persists even when power to the flash memory is turned off. This persistent characteristic of flash memory makes flash memory useful for data storage in applications such as PC bios, set-top boxes, printers, and network servers. In recent years, flash memory has also been widely used in portable devices such as digital cameras and mobile phones.
In an electrically erasable programmable read-only memory (EEPROM) type flash memory device capable of electrically erasing data in memory cells on a batch or sector basis, channel hot electrons are formed on the drain during programming. These channel hot electrons then accumulate on the floating gate, thus increasing the threshold voltage of a cell transistor. However, during erasure of the flash memory device, a high voltage is generated between the source/drain/substrate and the floating gate and electrons accumulated on the floating gate are discharged, thus lowering the threshold voltage of the cell transistor.
Cell structures of EEPROM type flash memory devices are classified as either an EEPROM thin oxide (ETOX) of a simple stack structure, or a split gate type cell including two transistors per cell. The ETOX cell structure has a structure in which a floating gate and a control gate are stacked. The split gate type cell structure has a structure in which a select transistor and two cell transistors are used, along with a control gate. One part of the control gate is overlapped with a floating gate and another part of which is disposed on a substrate.
FIG. 1 is a cross-sectional view of a conventional flash memory device fabricated according to a conventional method. As disclosed in FIG. 1, a conventional ETOX cell transistor is constructed by, first, sequentially stacking a tunnel oxide layer 12, a floating gate 14, an inter-gate insulating layer 16, and a control gate 18 on an active region of a semiconductor substrate 10. A source/drain 20 is then formed within the semiconductor substrate 10 on either side of a channel region positioned under the floating gate 14.
In the conventional flash memory device of FIG. 1, during programming a programming voltage is applied through word lines connected to the control gate 18 and bit lines connected to the source/drain 20. Electrons of the source/drain 20 are injected into the floating gate 14 through the tunnel oxide layer 12 in a hot carrier manner, so that programming of the cell transistor is performed. During erasure an erase voltage is applied through source lines connected to the source/drain 20. The electrons injected into the floating gate 14 are again discharged toward the channel through the tunnel oxide layer 12 to lower the threshold voltage of the cell transistor.
Unfortunately, as flash memory devices become increasingly integrated, data retention becomes increasingly problematic. In order to overcome this data retention problem, the floating gate and the control gate are sometimes covered with a gate insulating layer, and the sidewalls are covered with a sidewall oxide layer and a spacer nitride layer.
However, traps may result at the interface region due to damage that occurs when the floating gate of the sidewall parts is etched during the formation of the sidewall oxide layer. As electrons become trapped in the floating gate, data retention characteristic deteriorates.